The source of a PMOS transistor is positively charged with regard to its drain during operation. This positive source voltage can be problematic in that a p-n junction exists between the source and the n-well for the PMOS transistor. If the source is biased sufficiently higher than the n-well, this p-n junction is then forward biased. A conducting parasitic structure results from this forward biased p-n junction and the ground connection to adjacent NMOS transistors. The resulting short circuit condition in the conducting parasitic structure is referred to as latchup. Latchup is dangerous in that a circuit can be destroyed from the latchup currents. Moreover, even if the circuit can withstand the short circuit, latchup inhibits normal operation.
To prevent latchup, it is conventional to tie the n-well for a PMOS transistor to the highest expected source voltage. For example, if a PMOS transistor can operate in a low voltage mode and also in a high voltage mode, it is conventional to tie the PMOS n-well to the high voltage supply used during the high voltage mode operation. But the n-well tie is problematic as transistor dimensions are reduced such as in deep sub-micron technology. At these modern high-density process nodes, the gate oxide is too thin and the transistor is too small to handle the stress resulting from tying the n-well to a relatively high voltage supply.
To solve the latchup problem for PMOS transistors in modern process nodes that can operate in both high and low voltage modes, it is conventional to use robust PMOS transistors. In other words, the transistor dimensions are increased and a relatively thick gate-oxide is used. Such a large and thick gate-oxide PMOS transistor can then have its n-well tied to the high voltage supply without stressing the transistor. But the large transistor dimensions demand a lot of die area relative to the smaller transistor dimensions used in modern process nodes.
To increase density, n-well switching circuits have been developed that switch the n-well potential depending upon the PMOS transistor's voltage mode of operation. During low voltage operation, the PMOS transistor is powered by a low voltage supply so the n-well switching circuit biases the n-well to the low voltage. In this fashion, the n-well cannot become forward biased with regard to the PMOS source since both are tied to the same low voltage. But during high power operation, the PMOS transistor is powered by a high voltage supply such that the n-well switching circuit biases the n-well to the high voltage. Again, the n-well cannot become forward biased with regard to the PMOS source since both are then tied to the high voltage. Since the potential for the n-well switches between the low and high voltages depending upon the mode of operation, it may be denoted as a switched n-well.
One type of n-well switching circuit biases the switched n-well in low power operation using a native NMOS transistor. The native NMOS transistor does not include an n-well but instead is formed in the p-type substrate. This is advantageous because there is no resulting p-n junction in the native NMOS transistor that can become forward biased if the switched n-well is biased to the high voltage during high power operation. But deep sub-micron semiconductor processes may not be able to support the production of native transistors.
Accordingly, there is a need in the art for latchup prevention architectures with increased density that do not include native transistors.